In communications systems, a transmitter sends data streams to a receiver in symbols, such as bits of data. As the receiver clock is typically not synchronized with the transmitter clock, the receiver needs to correctly recover the clock from the received signal itself. In addition, when data is transmitted over a communication channel, it is usually distorted in terms of phase and amplitude due to various types of noise, such as fading, oscillator drift, frequency and phase offset, and receiver thermal noise. At the receiver, the system is also subject to noise and timing jitter in a time domain. Therefore, the receiver needs a timing recovery process to obtain symbol synchronization, particularly to correct the clock delay and derive the optimal clock phase that is used to sample the received signal and achieve the best Signal-to-Noise Ratio (SNR).
The distortion and noise introduced through signal propagation over a communication channel are characterized in terms of channel response, which is usually frequency and time-dependent. The receiver determines the channel response and accordingly compensates for the channel distortion and noise through a channel estimation process. The transmitted signal usually includes a reference signal (the so-called “pilot signal”) or a training sequence for channel estimation purposes. Typically, a channel estimator determines the channel response (or channel impulse response) on the particular carrier frequency and time instant by comparing the actual received signal with an expected signal, e.g., one that the receiver would have received under ideal channel conditions.
FIG. 1 illustrates the configuration of a timing recovery loop 100 in a receiver according to the prior art. As illustrated, the timing recovery loop 100 includes an Analog-to-Digital Converter (ADC) 110, an equalizer 111, a channel estimator 112, a delay element 113, a phase detector 114, a loop filter 115, and a Voltage Controlled Oscillator (VCO) 116. A received analog signal Rx 101 is converted to a digital signal dk′ 102 and then supplied to the equalizer 111 and the delay element 113. The equalizer 111 is used to render a flat frequency response in the signal and output an equalized signal and after slicing at the slicer 151, outputting the estimated symbol ak 103. The estimated symbol ak 103 is supplied to the channel estimator 112 to generate an estimated signal dk 104.
The channel estimator 112 includes channel response logic that correlates the signal transmitted from the transmitter (or “the transmitted signal”) and the received signal 101 at the receiver by using a mathematical relation of a set of coefficients. Thus, the estimated signal dk output from the channel estimator 112 is an estimation of the transmitted signal that incorporates the channel response. The delay element 113 delays the digital signal dk′ 102 to output symbols that have been processed by the timing loop 100, and thereby their characteristics have become known to the loop 100.
The phase detector 114 generates a phase error based on the difference between the delayed signal output from the delayed element 113 and the estimated signal dk 104. The loop filter 115 averages the phase error. The VCO adjusts the effective sampling frequency and phase based on the average phase error. As a result, a recovered clock signal 106 is generated from the VCO 116 and, in turn, used to clock the ADC 110 for sampling as well as to clock downstream processing logic. The performance of symbol synchronization can be indicated by a SNR or other parameters related to the noise level in the data stream.
The channel estimator 112 may include a Finite-Impulse-Response (FIR) filter composed of multiple filter taps. The multiple filter taps correspond to a number of consecutive samples used to generate an estimated sample. Conventionally, the channel estimator fixes the coefficients of a channel estimation filter, for example, by setting fixed tap weights of the FIR filter. The fixed tap weights may be configured based on known or estimated characteristics of the channel. Unfortunately, fixed channel estimation is incapable of adapting to time-varying channel response, resulting in possible large channel estimation errors.
Further, when a channel estimator applies an estimated channel response to generate an estimated signal, the channel estimator may correct the clock delay in the signal. This correction may undesirably interfere with the clock recovery process by the overall timing recovery loop, e.g., to be performed by a phase detector, a loop filter and a VCO in the same timing recovery loop. Particularly, the interference may cause recovered data symbols to shift from their optimized locations.